What is Avalanche Test of Power MOSFETs? (Part 3)

Hello everyone.
I’m Nakamatsu from the Power Device Design Section.

This is a sequel to my last blog that explained the avalanche capability tests for power MOSFETs.

In the previous article, I explained that even if the avalanche energy is the same, the junction temperature Tj of the MOSFETs are different under different test conditions, and thus avalanche capability cannot be simply compared. Now, let’s consider case (3), with L load value L=3 µH and avalanche current IAS=50 A for the same device as in the last blog.

Avalanche period tAV is expressed by the following equation:

 

 

Assuming avalanche voltage BVDSS=600 V and supply voltage VDD=300 V, we obtain tAV =500 ns in case (3). (This value may not be realistic, but just for case study we will proceed as it is.)

 

Using the equation appeared in previous article, we can calculate Tj :

 

 

Judging from the calculated Tj value below 150°C, the avalanche energy EAS is in an acceptable range according to the previous article. However, when we actually conducted an avalanche withstand test, the MOSFET was destroyed at IAS =50 A. Can you guess why that is?

 

Although I did not tell you this, we only considered the destruction mode by energy in the last time blog, but as a matter of fact there is another mode of destruction by current.

Figure 1 shows the structure and equivalent circuit diagram of an n-channel power MOSFET. The n-channel MOSFET innately has a parasitic npn transistor Tr and a parasitic diode D caused from its structure. Usually, this transistor Tr is designed not to be turned on. However, when the parasitic diode D of the MOSFET reaches avalanche operation due to exposure to high voltage, etc., an avalanche current flows through the resistor Rb, creating a potential difference VRb in Rb. When this potential difference VRb becomes large, avalanche current flows also to the base of the parasitic transistor Tr, causing the Tr to turn on, and a large current flows from its collector to emitter, leading to the destruction of the device. This is the mechanism of destruction mode by electric current.

 

Fig. 1 Structure of n-channel MOSFETs and parasitic transistor

 

In order to distinguish the destruction modes and examine the actual value of avalanche capability, it is often measured by changing the L values, and plotted the IAS value at the time of destruction and the L value on a double logarithmic graph.

Figure 2 shows an example of the measurement results with this device. The red X mark is the actual measured value and the orange line is the interpolated result. (This time, in the destruction-by-energy region, the avalanche capability is plotted at the line where Tj reaches 150°C, rather than at the actual value where the device destroys.)

 

Fig. 2 Relationship between L and IAS at Avalanche Destruction

 

In the region where L is less than 4.7 µH, the IAS is almost constant, indicating destruction by current. On the other hand, in the region where L is greater than 4.7 µH, the slope of the graph is -1/3, indicating that IAS is inversely proportional to 1/3 power of L. This means that in this region, the device is destructed by energy. In this way, by changing and measuring the L-load conditions, the failure mode can be identified and the avalanche capability can be estimated at each L-load value.

 

WTI has a special test environment for power devices and engineers with rich expertise for special tests, so please contact us if you need evaluation of various power devices, including avalanche capability tests.

 

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